Value reuse is an optimization process that eliminates redundant calculations or memory operations in a computer program by caching the output results of previous executions of complex instructions, a group of instructions, or even software functions. In cases where the value reuse technique is successful (the sought results do exist in the value cache), the value reuse technique may drastically reduce computation time and electrical power consumption of the target computer system by only performing a specific operation at a time (for example the value lookup operation).
However, as it can be recognized by those skilled in the art, the value reuse technique may add time and electrical power consumption overheads to a computer program and system. The overheads may include testing the value cache prior to executing the target instructions, groups of target instructions or target software functions plus the overheads of storing and retrieving the results. In other words, the potential benefits of a value reuse mechanism not only depend on the number of instances it has eliminated, but, inter alia, on the time and electrical power spent in detecting the instances to be eliminated.
The technology disclosed in this application targets to increase the payback (measured either in terms of electrical power savings, or as performance improvements, or both) from utilizing value reuse techniques especially in the context of graphics applications rendering 3-D data. The applicants believe therefore that there remains scope for improvements to value reuse techniques and similar operations in graphics processing systems. Thereby, it is desirable to provide new methods and apparatus (according to the technology disclosed in the present invention) for facilitating further electrical power savings and performance improvements when value reuse techniques are employed.
There have been proposed several disclosed methods that utilizing the value reuse technique for performance improvements. For example US2013/0073837, US2013/0074057, and US2011/0302371, where the applicants apply the value reuse technique at the boundaries of the application source code functions and they try to optimize the performance payback by statically selecting the most appropriate functions to perform memorization and by memorizing and reusing the results of the most frequently requested input parameters. U.S. Pat. No. 5,774,386 where the inventors break a color transformation function into subfunctions and the intermediate results of each subfunction are used for memorization.
The applicants believe that the value reuse techniques in prior art differs from what is disclosed in this application in at least five reasons.
First, the applicants propose to extend the instruction set architecture (also known as ISA) of the computing system intended to employ the technology disclosed in the present application with new instructions (also known as specifications) dedicated for the operation and the management of the value cache.
Second, the applicants propose to extend the processing path (also known as data path) of the computing system intended to employ the technology disclosed in the present application with a new, special purpose functional unit dedicated to perform value reuses.
Third, the applicants disclose methods and techniques utilizing an electrical power minimization approach to identify appropriate points in the source code of the applications and insert on those points the value cache management instructions.
Fourth, a hardware mechanism is disclosed which may monitor the dynamic behavior of an executing computer program and specific means are provided to deactivate and reactivate the value cache operation during the execution of the specific computer program.
Fifth, the value cache storage area is augmented with extra functionalities, e.g., to dynamically change the order of the executing instructions of the executing computer program.